In recent years, flash EEPROM has been widely used for various systems in industrial fields and public welfare fields because it has the advantages of being able to electrically erase and program data and being highly resistive to a shock as compared with a hard disk or the like.
To date, memory cells performing programming by CHE (channel hot electron) have been mainly employed. However, with increasing demands for a low voltage and a single power supply to the flash EEPROM, memory cell devices performing programming and erasing by FN (Fowler-Nordheim) tunneling have been developed.
FN tunneling has advantages over CHE in that the programming current is sufficiently low and a single power supply is realized by programming from a booster power supply. However, it requires several msec as a programming time per cell, and this is several tens to several hundreds times as long as the programming time of CHE.
In order to solve this problem, a page programming method is employed, in which a data latch is provided for each bit line to latch one word line of data and, simultaneously, programming and program verify are carried out.
In program verify, it is verified whether programming to the memory cells has been satisfactorily performed or not. If program verify is performed units of word lines, programming is repeated until memory cells for which programming has not been satisfactorily performed complete programming, and this causes a problem relating to reliability, such as drain disturbance.
In order to avoid this problem, there is proposed a method in which data stored in the latches connected to the memory cells for which programming has been completed are rewritten so that further programming is not performed on these memory cells.
Hereinafter, an example of program verify by the conventional flash EEPROM will be described with reference to FIG. 23.
FIG. 23 is a diagram illustrating a column latch circuit included in the above-mentioned DINOR flash EEPROM. In FIG. 23, L1 is a latch for storing data to be programmed. TG is a transfer gate which electrically separates a main bit line MBL0 from the latch L1. P1 and P2 are transistors for precharging the bit line according to the data stored in the latch L1 and a /PCO signal. SG0 is a select transistor which electrically separates the main bit line MBL0 from a sub bit line SBL0. Likewise, SG1 is a select transistor which electrically separates a main bit line MBL1 from a sub bit line SBL1. MEM0 and MEM1 are memory cells having control gates connected to a word line WL, sources connected to a source line SL, and drains connected to the sub bit lines SBL0 and SBL1. The source line SL is grounded when an ASL signal becomes active. RS1 and RS2 are transistors for resetting the main bit lines, and the main bit lines are grounded by RSO and RSE.
Next, the operation of the column latch circuit so constructed will be described.
Although the circuit shown in FIG. 23 has two main bit lines MBL0 and MBL1, programming and program verify on the main bit line MBL0 side will be described hereinafter.
Initially, when input data is latched by the latch L1, the supply voltage Vpp of the latch L1 is maintained at Vcc level. After all the data is latched, Vpp is increased to 6V which is the programming voltage of the memory cell. At this time, the selected word line WL is maintained at -8V while the control signal SGL of the select gate SG0 is maintained at 10V. Next, the transfer gate TG becomes active, and the latch L1 and the main bit line MBLO are electrically connected. When the data held by the latch L1 is "1", 6V is applied to the main bit line MBL0, and when it is "0", 0V is applied to the main bit line MBL0. Since -8V is applied to the control gate of the memory cell MEM0, when 6V is applied to the drain, an electric field occurs in the tunnel oxide film, and electrons stored in the floating gate are drawn to the drain side by an FN current. On the other hand, when the drain is at 0V, programming to the memory cell is not carried out because the electric field does not reach the strength at which a tunnel current occurs.
In program verify, Vpp is at Vcc level, and a voltage of Vcc level is applied to the main bit line MBL0 from the precharging transistors P1 and P2 in accordance with the data stored in the latch L1.
Next, a verify voltage of 1.5V is applied to the word line WL of the memory cell, and the source line SL is grounded by the enable signal ASL. When the threshold voltage of the memory cell is lower than 1.5V, discharging of the main bit line MBL0 is performed through the memory cell and the latch L1 detects it. At this time, the data in the latch L1 is rewritten and further programming is not performed. If the threshold voltage is higher than 1.5V, the initially set data is maintained as it is in the latch L1, and programming is performed until the data in the latch L1 is rewritten.
In the above-described construction, however, since the latched data must be rewritten by lowering the voltage of the main bit line by the memory cell current, stable verify is not achieved.
That is, the transistor of the latch L1 is able to supply a current larger than the sum of the values of the following currents: inter-band tunnel current which occurs between the drain and the substrate during programming, FN tunnel current, and leakage current from non-selected memory cells. However, in program verify, since the voltage of the control gate of the memory cell is a low voltage in the vicinity of the threshold voltage of the programmed memory cell, a sufficient cell current cannot be not secured, resulting in a problem that the latched data cannot be rewritten.